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IIT Guwahati develops secure Integrated Circuits for next-generation computing

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New Delhi, May 11: Researchers at the Indian Institute of Technology (IIT), Guwahati have developed technology for the design of fast, secure and dependable integrated circuits (ICs) for faster and efficient computing.

According to the team, the research looks at all aspects of the automated electronics design process like synthesis, verification and security, and contributes towards strengthening the electronics manufacturing ecosystem in our country.

With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs.

While multi-core processors are being used in modern times, their computing power improvements continue to be insufficient, the team claimed.

"A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualization processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks," said Chandan Karfa, Associate Professor, Department of Computer Science and Engineering, IIT Guwahati.

The team emphasised on hardware acceleration specifications that are often written in high-level languages like in C and C++ and are converted to hardware code (or register transfer level or Register-Transfer Level (RTL code), in a process called High-Level Synthesis (HLS).

Due to the complex conversation process, HLS translation may introduce bugs in the design and, therefore, stringent validation steps are required. The RTL simulators are used to validate HLS, but these are slow and complex.

"We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators. The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features."

"In addition to these simulators, prototypes of which are available for testing, the team has also developed a technology called HOST, which protects Integrated Circuits from IP theft during the design cycle. It has been shown to be resilient to any known attack till date," he added.

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IIT Guwahati develops secure Integrated Circuits for next-generation computing

New Delhi, May 11: Researchers at the Indian Institute of Technology (IIT), Guwahati have developed technology for the design of fast, secure and dependable integrated circuits (ICs) for faster and efficient computing.

According to the team, the research looks at all aspects of the automated electronics design process like synthesis, verification and security, and contributes towards strengthening the electronics manufacturing ecosystem in our country.

With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs.

While multi-core processors are being used in modern times, their computing power improvements continue to be insufficient, the team claimed.

"A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualization processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks," said Chandan Karfa, Associate Professor, Department of Computer Science and Engineering, IIT Guwahati.

The team emphasised on hardware acceleration specifications that are often written in high-level languages like in C and C++ and are converted to hardware code (or register transfer level or Register-Transfer Level (RTL code), in a process called High-Level Synthesis (HLS).

Due to the complex conversation process, HLS translation may introduce bugs in the design and, therefore, stringent validation steps are required. The RTL simulators are used to validate HLS, but these are slow and complex.

"We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators. The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features."

"In addition to these simulators, prototypes of which are available for testing, the team has also developed a technology called HOST, which protects Integrated Circuits from IP theft during the design cycle. It has been shown to be resilient to any known attack till date," he added.